Functional verification in chip design is the task of verifying that the chip conforms to specification. This is a complex task, and takes the majority of time and effort in most processor and electronic system design projects. Logic simulation may be used to simulate the logic before it is built. Simulation acceleration may be used to apply special purpose hardware to logic simulation. Emulation may be used to build a version of the system using programmable logic. This is expensive, much slower than the real hardware, but orders of magnitude faster than simulation. Formal verification may also be used to prove mathematically that certain requirements are met, or that certain undesired behaviors (such as deadlock or errors) do not occur.
However, design verification is becoming increasingly difficult as processor and electronic system complexity increases. As a result, it is likely that a chip will be sold before a bug (i.e. a problem) can be detected. More than likely, a bug will first be detected by a customer running an application using the chip. Faulty chips in the field can result in recalls of thousands to millions of chips, resulting in heavy financial losses and inconvenience to both the manufacturer and the customer. What is needed is systems and methods to overcome the above mentioned deficiencies in the field without having to recall the chips.